This work studies the viability of using a small reuse-driven cache, the ACDC, to enhance the first level of high-performance systems (HPC) cache hierarchy. Two ACDC organizations are tested: sequential and parallel. The ACDC has been evaluated at the hardware design level, implementing and integrating the ACDC in an open-source RISC-V core and in simulation using the gem5 architectural simulator. Presenting how the ACDC can be integrated into the hardware and evaluating performance and energy consumption results. The evaluation concludes that the ACDC could be a cheap addition in embedded HPC designs for optimizing energy (sequential organization) and performance (parallel organization).
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